With the continued emphasis on highly integrated electronic devices, there is an ongoing need for semiconductor memory devices that operate at higher speeds and lower power and that have increased device density. To accomplish this, devices with aggressive scaling and multiple-layered devices with transistor cells arranged in horizontal and vertical arrays have been under development.
As devices continue to become more aggressively scaled, the timing of the exchange of signals becomes more critical. In particular, in memory systems, arrangement of the timing of command/address signals, clock signals, and data strobe signals must be addressed as clock frequencies increase. In one example, in a memory system including a memory controller and a memory module having memory devices, the timing of signals being transferred to different memory devices on a given memory module can be different, due to a differing path length of the signal lines to each memory device on the memory module.
In particular, in contemporary memory systems, during a write operation of data signals to the memory devices, a write leveling procedure is performed to ensure that the clock signals and the data strobe signals reach each memory device on the module within a proper timing window. To perform write leveling operation, each memory chip includes its own “replica path” circuit which replicates the pathway transcended by the clock signals and the data strobe signal. A difference in phase is detected between the received clock signals and the received data strobe signal, and is transmitted to the memory controller. During a later write operation to one of the memory chips on the module, the memory controller delays the data strobe signal so that it and the clock signals reach the memory chip at the same time.
As operating frequencies continue to increase, a write leveling operation performed using a replica path is insufficient for controlling signal timing within tight timing constraints. In addition, the replica path consumes circuit area on the memory chip, which is at a premium in highly integrated devices. Further, a replica path can be wasteful of system power resources.
In addition, in contemporary systems, the phase comparison used for write leveling is made between a buffered clock signal of the clock signal received from the memory controller and the buffered data strobe signal of the data strobe signal received from the memory controller. The clock signal is periodic and continuously toggling with a predetermined duty cycle. Therefore, it is difficult to align the data strobe signal with the free-toggling clock signal, since only a half cycle (0.5 tCK, assuming the clock signal has a 50:50 duty cycle ratio) calibration margin for each direction is available for aligning them at the same rising or falling edge.
Furthermore, the amount of the skew caused by the device interface and internal circuits has a fixed value. At the same time, the clock cycle becomes smaller as operating frequencies increase. This can further introduce limitations when the conventional write leveling operation is performed.